An integrated circuit (IC) is an electronic circuit formed using a semiconductor material, such as Silicon, as a substrate and by adding impurities to form solid-state semiconductor electronic devices (device, devices), such as transistors, diodes, capacitors, and resistors. Any reference to a “device” herein refers to a solid-state semiconductor electronic device unless expressly distinguished where used. Commonly known as a “chip” or a “package,” an integrated circuit is generally encased in hard plastic, forming a “package.” The components in modern day electronics generally appear to be rectangular black plastic packages with connector pins protruding from the plastic encasement. Often, many such packages are electrically coupled so that the chips therein form an electronic circuit to perform certain functions.
The software tools used for designing ICs produce, manipulate, or otherwise work with the circuit layout and circuit components on very small scales. Some of the components that such a tool may manipulate may only measure tens of nanometer across when formed in Silicon. The designs produced and manipulated using these software tools are complex, often including hundreds of thousands of such components interconnected to form an intended electronic circuitry.
A layout includes shapes that the designer selects and positions to achieve a design objective. The objective is to have the shape—the target shape—appear on the wafer as designed. However, the shapes may not appear exactly as designed when manufactured on the wafer through photolithography. For example, a rectangular shape with sharp corners may appear as a rectangular shape with rounded corners on the wafer.
Once a design layout, also referred to simply as a layout, has been finalized for an IC, the design is converted into a set of masks or reticles. A set of masks or reticles is one or more masks or reticles. During manufacture, a semiconductor wafer is exposed to light or radiation through a mask to form microscopic components of the IC. This process is known as photolithography.
A manufacturing mask is a mask usable for successfully manufacturing or printing the contents of the mask onto wafer. During the photolithographic printing process, radiation is focused through the mask and at certain desired intensity of the radiation. This intensity of the radiation is commonly referred to as “dose”. The focus and the dosing of the radiation has to be precisely controlled to achieve the desired shape and electrical characteristics on the wafer.
A device generally uses several layers of different materials to implement the device properties and function. A layer of material can be conductive, semi-conductive, insulating, resistive, capacitive, or have any number of other properties. Different layers of materials have to be formed using different methods, given the nature of the material, the shape, size or placement of the material, other materials adjacent to the material, and many other considerations.
The software tools used for designing ICs produce, manipulate, or otherwise work with the circuit layout and circuit components on very small scales. Some of the components that such a tool may manipulate may only measure a few nanometers across when formed in Silicon. The designs produced and manipulated using these software tools are complex, often including hundreds of thousands of such components interconnected to form an intended electronic circuitry.
A Field Effect Transistor (FET) is a semiconductor device that controls the electrical conductivity between a source of electric current (source) and a destination of the electrical current (drain). The FET uses a semiconductor structure called a “gate” to create an electric field, which controls the shape and consequently the electrical conductivity of a channel between the source and the drain. The channel is a charge carrier pathway constructed using a semiconductor material.
Many semiconductor devices are planar, i.e., where the semiconductor structures are fabricated on one plane. A non-planar device is a three-dimensional (3D) device where some of the structures are formed above or below a given plane of fabrication.
A fin-Field Effect Transistor (finFET) is a non-planar device in which a source and a drain are connected using a fin-shaped conducting channel (fin). A vertical channel device is a device in which the current travels from a source to a drain in a direction that is substantially orthogonal to the plane of fabrication, e.g., the plane of the substrate material. A finFET can be constructed as a vertical channel device whereby, a source or drain (S/D) is formed in or near the plane of fabrication, a fin is fabricated substantially perpendicular to the plane of fabrication, and another S/D is fabricated above the fin. A finFET with a vertical channel is referred to herein as a vertical finFET.
The S/D that is in or near the plane of fabrication is referred to herein as the bottom S/D. The other S/D is referred to as the top S/D. The side of the bottom S/D that is facing the substrate (and is opposite to the side connecting to the fin) is referred to herein as the backside of the device.
In a FET, a gate controls the current flow between the two S/D through the fin. The direction along the vertical length of the fin (perpendicular to the plane of fabrication) running from one S/D to the other S/D is referred to herein as a vertical running direction of the fin. The direction of the current flowing between the two S/D through the fin is therefore substantially perpendicular to the plane of fabrication.
A CB contact is an electrical connection to a gate. A circuit external to the finFET uses the CB contact to electrically connect a part of the circuit to a gate in the finFET.
A TS contact is an electrical contact that provides electrical connectivity to an S/D. A circuit external to the finFET uses the TS contact to electrically connect a part of the circuit to a S/D in a vertical finFET.
The illustrative embodiments recognize that the present methods and techniques for fabricating a vertical finFET suffer from several problems. For example, presently, the TS contact for the bottom S/D is connected to the same side or surface of the bottom S/D to which the fin is connected. This manner of placing the TS contact is necessitated by the fact that once formed, the backside of the bottom S/D not being accessible for TS contact placement.
The illustrative embodiments recognize that placing the TS contact on the same surface as the fin on the bottom S/D greatly increases the distance the electrical current has to travel through the bottom S/D. The current travels down the TS contact, down through the bottom S/D, across the distance from the location of the TS contact to the location of the fin, and up through the bottom S/D to enter the fin. This down-and-up path through the bottom S/D significantly increases the resistance faced by the electrical current in the bottom S/D.
The illustrative embodiments recognize that if the TS contact could be electrically connected to the backside of the bottom S/D, the electrical current would only have to travel from the TS contact up through the bottom S/D to enter the fin. Thus, the electrical path through the bottom S/D, and consequently the resistance of the bottom S/D would be significantly reduced. Therefore, the illustrative embodiments recognize that some manner of accessing the backside of the bottom S/D is desirable.
The illustrative embodiments further recognize that accessing the backside of the bottom S/D is further exacerbated by the gate fabrication process. Even though this is not how the vertical channel devices are presently fabricated, even if some connectivity were maintained with the backside of the bottom S/D during the fabrication process, the gate construction step would destroy or damage such connectivity. The illustrative embodiments recognize that gates use a metal, and the fabrication of the gate is a high temperature step that would be detrimental to any connecting apparatus that could be pre-fabricated at the backside of the bottom S/D.
Therefore, any connectivity to the backside of the bottom S/D should be fabricated after the gates have been fabricated. Therefore, a method for fabricating access to the backside of the bottom S/D after the gates have been fabricated would be desirable.